With a view to achieving higher integration and higher performance of an LSI circuit, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see, for example, Patent Document 1: JP 2-188966A). In the SGT, a drain, a gate and a source are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor.
FIGS. 37(a) and 37(b) are, respectively, a bird's-eye view and a sectional view showing an SGT disclosed in the Patent Document 1. With reference to FIGS. 37(a) and 37(b), a structure of the SGT will be described. A pillar-shaped silicon layer 501 is formed on a silicon substrate. A gate dielectric film 502 is formed to surround the pillar-shaped silicon layer 501, and a gate electrode 503 is formed to surround the gate dielectric film 502. A sidewall of the pillar-shaped silicon layer 501 surrounded by the gate electrode serves as a channel of a transistor. A lower diffusion layer 504 and an upper diffusion layer 505 each serving as a source/drain region are formed, respectively, in underneath and upper portions of the pillar-shaped silicon layer 501. The upper diffusion layer 505 is connected to an interconnection layer via a contact.
Patent Document 1: JP 2-188966A
In cases where the SGT illustrated in FIG. 37 as disclosed in the Patent Document 1 is applied to a highly-integrated and high-performance logic device, such as CPU, it is necessary to form a silicide layer in the source/drain region in a self-alignment manner to reduce a parasitic resistance of the source/drain region so as to improve transistor performance. In addition, it is critical to improve the transistor performance without increasing an occupancy area of the SGT.
In view of the above circumstances, it is an object of the present invention to reduce a film thickness of a silicon nitride film on an outer periphery of a gate electrode of an SGT to reduce an occupancy area of the SGT, and an occupancy area of a circuit formed using the SGT, particularly a circuit where the SGT and a contact are arranged with a minimum distance therebetween, such as an SRAM.